1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a semiconductor device which requires a high breakdown voltage, and a method of manufacturing the same.
2. Description of the Background Art
A semiconductor device of a type having a high breakdown voltage is characterized in that it has a high switching rate, operates safely over a large range, readily allows parallel operations, and so on. For these reasons, in recent years, attention is being paid to such semiconductor devices of the type having high breakdown voltages as well as to bipolar transistors and thyristors, as switching devices for power and the like.
As a conventional semiconductor device, a diode of a type having a high breakdown voltage will be described in the following.
FIG. 18A is a cross sectional view schematically showing the structure of the conventional semiconductor device. FIG. 18B is a schematic plan view taken from the direction of arrow A.sub.2 in FIG. 18A.
Referring to FIGS. 18A and 18B, an n.sup.- epitaxial layer 3 and a p.sup.+ diffused region 5 are formed on a surface of a p type semiconductor substrate 1. This p.sup.+ diffused region 5 forms an annular structure surrounding n.sup.- epitaxial layer 3, when viewed two dimensionally.
An n.sup.+ diffused region 7 is formed at a surface of n.sup.- epitaxial layer 3.
On surfaces of n.sup.- epitaxial layer 3 and p.sup.+ diffused region 5, a silicon oxide film 9 is formed. A contact hole 9a exposing a portion of the surface of p.sup.+ diffused region 5, and a contact hole 9b exposing a portion of the surface of n.sup.+ diffused region 7, are formed at this silicon oxide film 9.
A first electrode layer 11 is formed to be in contact with p.sup.+ diffused region 5 through contact hole 9a. This first electrode layer 11 is formed to have an annular configuration along the contour of p.sup.+ diffused region 5 when viewed two dimensionally. Also, a second electrode 13 is formed to be in contact with n.sup.+ diffused region 7 through contact hole 9b.
An interlayer insulating film 401 is formed, covering first and second electrode layers 11 and 13. This interlayer insulating film 401 consists of a single layer of silicon oxide film, and is formed to have an approximately uniform film thickness T.sub.1. A thorough hole 401a is formed in interlayer insulating film 401, reaching second electrode layer 13. This through hole 401a includes a hole 401b opened by isotropical etching and a hole 401c formed by anisotropical etching. An interconnection layer 19 is formed to be in contact with second electrode layer 13 through this through hole 401a, being spaced apart from first electrode layer 11 with interlayer insulating film 401 therebetween.
In addition, n.sup.+ diffused region 7 is formed by implantation of arsenic and p.sup.+ diffused region 5 is formed by implantation of boron.
Here, n.sup.- means that the amount of n type impurity implanted is relatively small, and n.sup.+ and p.sup.+ means that the amount of n type and p type impurities implanted respectively is relatively large.
A method of manufacturing the conventional semiconductor device will now be described.
FIGS. 19 to 25 are schematic cross sections illustrating the method of manufacturing the conventional semiconductor device, in the order of the steps which are to be performed. Referring first to FIG. 19, n.sup.- epitaxial layer 3 is formed on the surface of p type semiconductor substrate 1. On the surface of this n.sup.- epitaxial layer 3, a thin silicon oxide film (not shown) is formed, which is patterned to a desired shape. Using this thin silicon oxide film as a mask, deposition of boron (B) is performed so that boron is diffused within n.sup.- epitaxial layer 3. Thus, p.sup.+ diffused region 5 is formed, surrounding n.sup.- epitaxial layer 3 in an annular configuration. The thin silicon oxide film is then removed.
Referring to FIG. 20, a thin silicon oxide film 421 is formed on the surface of n epitaxial layer 3 in which p.sup.+ diffused region 5 has been formed. This thin silicon oxide film 421 is patterned by photolithography and etching to obtain a predetermined shape. Using this patterned silicon oxide film 421 as a mask, an n type impurity is implanted into n.sup.- epitaxial layer 3. By diffusion and activation of this n type impurity, n.sup.+ diffused layer 7 is formed at the surface of n.sup.- epitaxial layer 3. Silicon oxide film 421 is then removed.
Referring to FIG. 21, silicon oxide film 9 is formed on the surfaces of n.sup.- epitaxial layer 3 and p.sup.+ diffused region 5. A photoresist 423a is applied on the entire surface of this silicon oxide film 9, and then is subjected to exposure and development. In this way, resist pattern 423a having a hole pattern above p.sup.+ diffused region 5 and above n.sup.+ diffused region 7 is formed. Using this resist pattern 423a as a mask, silicon oxide film 9 is etched anisotropically, thereby forming contact holes 9a and 9b. From contact hole 9a, a portion of the surface of p.sup.+ diffused region 5 is exposed. A portion of the surface of n.sup.+ diffused region 7 is exposed through contact hole 9b. Thereafter, resist pattern 423a is removed.
Referring to FIG. 22, an AlSi (Aluminum Silicon) film is formed entirely on the surface of silicon oxide film 9 by sputtering. Then the Alsi film is patterned to a desired shape by photolithography and etching. In this way, first electrode layer 11 is formed to be in contact with p.sup.+ diffused layer 5 through contact hole 9a and would present an annular configuration when viewed two dimensionally. At the same time, second electrode layer 13 is also formed, being in contact with n.sup.+ diffused region 7 through contact hole 9b.
Referring to FIG. 23, interlayer insulating film 401 consisting of a single layer of thick silicon film is formed entirely on the surface of silicon oxide film 9 by, for example, plasma such that it covers first and second electrode layers 11 and 13 with an approximately uniform film thickness.
Referring to FIG. 24, photoresist 423b is applied on an entire surface of interlayer insulating film 401, and then is subjected to exposure and development. In this way, resist pattern 423b having a hole pattern above third electrode layer 13 is formed. Using this resist pattern 423b as a mask, an isotropic etching is performed on interlayer insulating film 401. Thus, the surface of interlayer insulating film 401 which exposes itself at the bottom portion of the hole pattern is etched isotropically, and hole 401b is formed.
Thereafter, anisotropic etching is performed until the surface of second electrode layer 13 is exposed, still using resist pattern 423b as a mask. This etching leads to the formation of second hole 401c at the bottom portion of first hole 401b. These first and second holes 401b and 401c constitute through hole 401a. Resist pattern 423b is then removed.
Referring to FIG. 25, an AlSi (Aluminum Silicon) film 19 is formed entirely over the surface of first interlayer insulating film 401 by sputtering. This AlSi film 19 is patterned by photolithography and etching. This patterning leads to the formation of interconnection layer 19 which comes into contact with second electrode layer 13 via through hole 401a and is opposed to first electrode layer 11 with interlayer insulating film 401 therebetween.
In general, an industrial power supply line may be an alternating current line of either 200V or 400V. The 200V alternating current line is mainly employed in Japan, and the 400V alternately current line is mainly employed in Europe. When rectified, this alternating current of 200V becomes direct current of 300V, and the alternating current of 400V becomes direct current of 600V.
In view of the above, driving an IC (Integrated Circuit) by a power supply with an alternating current 200V power supply involves a breakdown voltage of 600V or more in direct current for the IC as a whole, considering that surge voltage or the like would be applied. For a similar reason, an alternating current 400V power supply requires a breakdown voltage of 1200V or more for the whole IC.
In an IC employing an alternating current 400C power supply, there is a region in the IC where voltage varies in the range of 0 to 1200V. Accordingly, an interconnection which is lead out from this region would similarly have a potential of 0 to 1200V. Thus, at the portion where an interconnection of level 0V and an interconnection which would experience a rise in potential up to 1200V are crossed, the interconnection insulating film providing insulation between the two interconnections will require breakdown voltage of at least 1200V.
Thus, considering the differences among the standards in various countries, the breakdown voltage required for the interlayer insulating film which provides insulation between the interconnection layers would be very high.
Accordingly, film thickness T.sub.1 of interlayer insulating film 401 have to be increased at the region where interconnection layer 19 and first electrode layer 11 are opposite to each other, as shown in FIG. 18A. In particular, film thickness T.sub.1 of interlayer insulating film 401 must be no less than 2 .mu.m.
In the conventional semiconductor device, however, the entire interlayer insulating film 401 is formed to have a practically uniform film thickness. Thus, there has been a problem that the increase in the film thickness of interlayer insulating film 401 leads to the increase of chip size, as will be explained in detail in the following.
Referring mainly to FIG. 18A, in order to connect interconnection layer 19 to second electrode layer 13, it is generally necessary to provide through hole 401a in interlayer insulating film 401. When film thickness T, of interlayer insulating film 401 is increased, the depth of the through hole is also increased. Accordingly, on the assumption that the through hole is formed by anisotropic etching only as shown in FIG. 26, the aspect ratio (depth/opening width) of a through hole 401d is increased. The increase of the aspect ratio degrades the step coverage of interconnection layer 19 formed within through hole 401d. Especially when interconnection layer 19 is formed by sputtering, there is a possibility of disconnection of the interconnection layer 19 at the bottom portion of through hole 401d (that is, at region R.sub.1), since sputtering is poor at step coverage.
A method of present this disconnection of the film has been known in which interlayer insulating film 401 is etched at first isotropically and then anisotropically, as shown in FIG. 24.
According to this method, sidewall of hole 401b formed by isotropic etching would be smooth. Thus, the step coverage of interconnection layer 19 at this sidewall portion of hole 401b will be satisfactory.
In addition hole 401c formed by anisotropic etching comes to have a depth T.sub.2 made smaller by the amount corresponding to the depth of the isotropic etching performed. Accordingly, the aspect ratio of hole 401c is made smaller and the step coverage of interconnection layer 19 would be satisfactory even when it is formed by sputtering.
Based on the foregoing, according to the method described above, the step coverage of interconnection layer 19 in through hole 401a can be made satisfactory.
However, in the above method, isotropic etching causes an enlargement of a dimension L.sub.3 of the opening of through hole 401a. When dimension L.sub.3 of the opening is increased, it would be difficult to pattern the interconnection layer if, for example, the through holes are formed adjacent to one another.
FIG. 28 is a schematic cross section showing how the through holes may be formed adjacent to one another. FIG. 29 is for illustrating the difficulty caused in the patterning of the interconnection layer when dimension L.sub.3 of the opening is increased.
Referring first to FIG. 28, in order to ensure a satisfactory step coverage for interconnection layer 19 within hole 401c, depth T.sub.2 of hole 401c must not exceed a predetermined depth. Accordingly, when film thickness T.sub.1 of interlayer insulating film 401 is increased, it is necessary to increase a depth T.sub.3 of hole 401b also. In an isotropic etching, the amount of etching performed vertically and the amount of etching performed laterally are approximately the same. Accordingly, the increase in depth T.sub.3 of hole 401b essentially involves increase in width L.sub.3 of the opening. In other words, the larger the film thickness T.sub.1 of interlayer insulating film 401 is, the more increased is the dimension L.sub.3 of the opening.
In this case, holes 401b are connected with one another at the region between the adjacent through holes 401a. As a result, interlayer insulating film 401 would have a sharp pointed shape at region R.sub.3 where holes 401b are connected with one another. In such a region as R.sub.3, the patterning of interconnection layer cannot be performed accurately.
Accordingly, when film thickness T, of interlayer insulating film 401 is made very large, it is necessary to increase the space L.sub.5 between through holes 401a at least in such a manner that holes 401b will not be connected with one another. However, the increase in this space L.sub.5 causes increase in the layout area when viewed two dimensionally and thus involves increase in the chip size.